org 0x0

start:
    ;mov direct,#data
	mov 0x10,#0xaa
	mov DPTR,#0x1234
	;prepare
	mov R0,#0x20       ;R0=0x20
	mov 0x20,#0x11     ;(0x20)=0x11
	mov R1,#0x30       ;R1=0x30
	;MOV A,@Ri
	;MOV direct,@Ri
	mov A,@R0          ;a=(0x20)=0x11
	mov 0x21,@R0
	;MOV @Ri,a
	mov @R1,A          ;(0x30)=0x11
	;MOV @Ri,direct
	MOV R1,#0x31
	MOV @R1,0x20       ;(0x31)=(0x20)=0x11
	;MOV @Ri,#data
	mov R1,#0x32
	MOV @R1,#0x78       ;(0x32)=0x78
	;mov c,bit
	;mov bit,c
	mov PSW, #0x80        ;c=0x1
	mov 0x0, C
	mov R0,PSW
	mov PSW, #0x00
	mov R1,PSW
	
	sjmp $
	
	
;for test
REG_SP     EQU 0x1000
REG_A      EQU 0x1001
REG_B      EQU 0x1002
REG_PSW    EQU 0x1003
REG_PC     EQU 0x1004
REG_DPTR   EQU 0x1005
CYCLE      EQU 0x1006
REG_R0     EQU 0x2000
REG_R1     EQU 0x2001
REG_R2     EQU 0x2002
REG_R3     EQU 0x2003
REG_R4     EQU 0x2004
REG_R5     EQU 0x2005
REG_R6     EQU 0x2006
REG_R7     EQU 0x2007
REG_END    EQU 0x2FFF
	org 0x600
	dw 0x10,      0xaa
	dw 0x20,      0x11
 	dw 0x21,      0x11
	dw 0x30,      0x11
	dw 0x31,      0x11
	dw 0x32,      0x78
	dw REG_SP,    0x7
	dw REG_A,     0x11
	dw REG_B,     0x0
	dw REG_PC,    0x25
	dw REG_DPTR,  0x1234
	dw CYCLE,     29
	dw REG_R0,    0x80
	dw REG_R1,    0x0
	dw REG_R2,    0x0
	dw REG_R3,    0x0
	dw REG_R4,    0x0
	dw REG_R5,    0x0
	dw REG_R6,    0x0
	dw REG_R7,    0x0
	dw REG_END,   0
end
	